`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:09:42 11/02/2011
// Design Name:   VGA_Sync
// Module Name:   C:/Users/david/Desktop/16bitcpu/VGA_Writer_test.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: VGA_Sync
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module VGA_Writer_test;

	// Inputs
	reg clk;
	reg reset;

	// Outputs
	wire vga_v_sync;
	wire vga_h_sync;

	// Instantiate the Unit Under Test (UUT)
	VGA_Sync uut (
		.clk(clk), 
		.reset(reset), 
		.vga_v_sync(vga_v_sync), 
		.vga_h_sync(vga_h_sync)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;

		// Wait 100 ns for global reset to finish
		#100;
		reset = 1;
		#100 reset=0;
        
		// Add stimulus here

	end

	always  begin
		#20 clk=~clk;
	end
      
endmodule

